1. Field of the Invention
This invention generally relates to digital filtering and, more particularly, to a system and method for using a digital filter to enable an efficient switching response.
2. Description of the Related Art
A phase-locked loop (PLL) is often used as a phase conditioning circuit for mapping time domain multiplexed (TDM) signals. The PLL is used to attenuate phase variations between the input and output data streams to within acceptable (i.e., standardized) levels. Due to the stringent requirements on phase control, the bandwidth of such a PLL is usually very low, typically well below 1 Hz. While this narrow bandwidth is preferred for normal operation, it can be a problem if there is a change in the data rate, as can occur when there is a disruption in the network, a reorganization of the network, or during entry into and exit from alarm conditions. During these times there are other, competing demands that require the circuits to react within a short time. The PLL must detect condition changes and modify its behavior to lock on to the changed rate quickly, which requires a wide bandwidth. Once acquired, the PLL must attenuate the phase variations with the low bandwidth.
One specific application of the above-mentioned PLL involves timing transport over packet networks. Due to the large phase variations that may occur in packet networks, these PLLs must have ultra-low bandwidths in order to adequately regulate the recovered timing. As a consequence, the loop can take a very long time (from hours to days) to respond to rate changes. An alternate mechanism is therefore required to reduce this acquisition time, while still maintaining the behavior which conditions phase variation. Various mechanisms have been designed, and they usually involve changing the bandwidth of the filter in response to detecting a change in operating conditions.
FIG. 1 is a schematic block diagram depicting a phase conditioning circuit used for mapping (prior art). Incoming data goes into a buffer 10, and is read out by a rate generator 12, usually contained in a mapping circuit (not shown). The instantaneous buffer fill is sent to a filter 14, which sets the rate at which the rate generator reads out the data. These elements form a loop that serves to regulate the outgoing data rate.
FIG. 2 is a diagram depicting the buffer fill variation as a function of time when the loop is in a locked state (prior art). When the loop is locked, the output data rate is equal to the average input rate, such that the buffer 10 stays approximately half-full. Due to network impairments, the rate of the incoming data is not constant, but varies about its putative value. Therefore, instantaneously, the incoming rate is sometimes higher than its nominal rate and sometimes lower than its nominal rate. As a result, if the output rate is at the nominal value (as recovered by the loop), then the buffer fill has some variation, the average value of which is zero. So, the buffer is roughly centered, but can vary about the center value by the amount of the variation in the incoming and outgoing rates.
The maximum allowed variation in the incoming data rate is constrained by the communications standards. The high frequency variation is called jitter, and is usually of small magnitude. The low frequency variation is called wander, and can be of high magnitude. The wander typically has to be carefully controlled in order to prevent buffer overflows or underflows.
FIG. 3 is a diagram depicting buffer fill as a function of time when there is a change in the incoming data rate (prior art). When there is a change in the incoming rate, the buffer starts to fill (or empty), as shown. A non-temporary variation (e.g., a new data rate) must be distinguished from wander. Variations due to wander can be controlled by adjusting the rate of the outgoing data, while a new rate has an average trend that will either fill or empty the buffer.
Therefore, multi-speed loops and circuitry capable of detecting changes in incoming data rates are a conventional solution to the above-mentioned PLL issues. The trade-offs between underdamped and overdamped loops are well known in the art, and each condition is associated with a different set of problems. Further, in the case of a loop using a digital filter, the calculations required during these bandwidth transitions are very intensive, and in some cases, may lead to a loss of lock.
It would be advantageous if a digital filter response could be efficiently switched, without changing the filter design, but using a special set of non-calculation-intensive transient coefficients.